Generally, in semiconductor fabrication, wafers are operated on at a lot level, where a lot comprises one or more wafers. A wafer of a lot of one or more wafers comprises one or more die. Due to one or more variations in semiconductor processing, die within the same wafer or same lot may comprise slightly different characteristics. In order to compensate for the difference in characteristics between dies, statistical simulation is adopted to reflect the process variation during a design stage. One or more global variation factors will be generally applied for the simulation. However, simulation becomes more difficult with advanced technology